High performance high density semiconductor devices include devices with increasingly finer geometries. Accordingly, methods of fabricating these devices with small geometries (for example, in the sub-0.5 .mu.m range), must yield to exacting standards for handling minute tolerances associated with these small geometries. In fabricating semiconductor devices with such small feature dimensions, isolation between distinct regions of the devices must be maintained while achieving connectivity to selected regions of the device.
One conventional method for isolating semiconductor devices is local oxidation of silicon ("LOCOS"). In this process, the active regions of different semiconductor devices are isolated by thermally growing thick field oxide regions therebetween. However, the field oxide regions grown using LOCOS have sloped ends, forming a relatively large "bird's beak" at each end of the field oxide region. Because of the large "bird's beak" of the field oxide regions, an isolation structure formed using LOCOS may not be scaled to lower devices sizes. Thus, LOCOS is unsuitable for semiconductor devices having a smaller feature size.
Shallow trench isolation ("STI") is a conventional alternative to LOCOS for semiconductor devices having a smaller feature size. To form an STI isolation structure, a trench is etched in a semiconductor substrate. The trench has substantially vertical sidewalls. A dielectric such as tetraethylortho silicate (TEOS) is then deposited. The dielectric fills the trench, forming the STI isolation structure. Because the STI isolation structure is formed through an etch and dielectric deposition, the STI isolation can be scaled to semiconductor devices having smaller a feature size.
Once the isolation structures are formed either using LOCOS or STI, conventional semiconductor processing continues. Active regions are formed between the isolation structures. A dielectric layer is then provided. The dielectric layer covers the surface of the semiconductor devices, including the active regions and isolation structures. Electrical contact with the active regions is also made. Typically, contact holes are etched through the dielectric layer to the active surfaces. The contact holes are then filled with a conductor.
Semiconductor devices having isolation structures formed using either LOCOS or STI often suffer from misalignment of features such as contacts. In order to etch contact holes, a mask is provided on the dielectric layer. The mask may be misaligned. For example, a contact hole in the mask may lie above both an active region and an isolation structure. Moreover, the thickness of the dielectric layer varies across the surface of the semiconductor. To ensure that contact holes are provided regardless of the thickness of the dielectric layer, longer etch times are used. In areas where the dielectric layer is thinner, a portion of the isolation structure may be etched, exposing the semiconductor under the active region and adjacent to the isolation structure. When the contact hole is filled with the conductor, the conductor makes contact with both the active region and the underlying semiconductor. The active region and underlying semiconductor are shorted. Consequently, the semiconductor device may be inoperable.
For a semiconductor device having isolation structures formed using LOCOS, shorts due to contact misalignment are addressed using plug implants. Plug implants are used to dope the area of the underlying semiconductor at the edge of an isolation structure. When a misaligned contact hole is filled with the conductor, the conductor may reach the plug implant, but not the underlying semiconductor. Shorting between the underlying semiconductor and the active region is thereby prevented.
Although plug implants function for isolation structures formed using LOCOS, plug implants are inappropriate for isolation structures formed using STI. An STI isolation structure has substantially vertical sidewalls. Consequently, doping the underlying semiconductor at the edge of an STI isolation structure is virtually impossible.
Accordingly, what is needed is a method and system for reliably and consistently reducing problems due to misalignment of the contacts for a semiconductor device. Although applicable to many semiconductor devices, such a method and system would be particularly useful in semiconductor devices isolated using STI. It would also be beneficial if the method and system increase semiconductor devices fabrication throughput. The present invention addresses such needs.